During the process of making semiconductor chips, each manufactured semiconductor chip is a little bit different because of process variations. Designers need to create as many chips as possible that work in spite of these process variations. Process variations are a function of many variables, and the width, thickness, and inter-layer thickness can vary independently for each layer on a chip, as can temperature and voltage. Currently designers cope with these variations by designing circuits using traditional methods such as picking a few subsets of variations, called process corners, and analyzing performance at these corners. However, these approaches are both too conservative (the specified conditions will seldom occur) and not conservative enough (they miss errors that can occur due to process variation).
For example, building a chip is a sequence of hundreds of operations, each of which will occur a little differently on each chip despite enormous effort to make them repeatable. This variation occurs in many ways. First, there is variation from chip to chip, for example, often the logic on one chip is significantly faster than on another chip. In general, but not completely, these changes are correlated, i.e., if one gate is fast, then so are all the others on the same chip.
Variations in interconnect follow a different pattern. One machine, in one action, lays down all the metal (or dielectric) for a layer of a chip. A different machine, or the same machine at a different time, lays down the next layer. Thus the layers are not correlated to each other, but they are correlated across the chip. If metal-1 is thick, then metal-1 will be thick across the whole chip, but this implies nothing about the thickness of metal-2.
There is also variation across the surface of a chip. Some of this variation is deterministic. For example, the metal or inter-layer dielectric (ILD) thickness may depend on the local metal density. Two nominally identical lines, one in the center of the chip and one near the edge, may be built differently since the optics in the photolithography step has different responses in each area.
Finally, all of the above variations have a statistical component as well, due to manufacturing variations. This statistical component may vary depending on the distance between two objects on a chip. Two components close to each other on a chip are likely to be closely matched, whereas two components further away will have larger differences.
Process variation occurs in a space of roughly ND=2+3+2+3N dimensions, where N is the number of routing layers. The first two dimensions are the (X, Y) coordinates within the chip. Each of the remaining process variables may assume a value that depends on this location. The next 3 variables are for the cell performance, perhaps diffusion width, poly width, and oxide thickness. The next two variables are for voltage and temperature. For the purpose of this discussion they can be treated as process variables. The remaining 3N dimensions occur because for each routing layer there are three main variables, metal thickness, metal width, and inter-layer dielectric thickness. Note that the metal width and metal spacing do not vary independently. Their sum, the pitch, is extremely well controlled.
Since working in 30 or so dimensions is difficult, designers have made various approximations. First, the variation of process with (X,Y) coordinate has been largely ignored, as has deterministic variation (though this is changing). Next, the number of process variation combinations is reduced to a small number of “process corners”. A process corner sets all relevant variables to an extreme (usually 3σ) value. This corresponds to a corner of a hypercube in the real process space. There are 2ND process corners—far too many to analyze (much less the interior points). Since timing is the most important result, designers usually characterize the interconnect and cells as ‘fast’ or ‘slow’. Cell speed and interconnect speed are largely independent since the variables that affect cell delay have very little effect on interconnect delay, and vice-versa.
This approach assumes that the most extreme delay cases will be the worst. One worst case will be with slow cells and slow interconnect; this will be used for checking for setup time problems. Fast cells and fast interconnect will be used for checking for hold problems. The two interconnect cases are obtained by using two extractions—one at fast interconnect corner, one at the slow interconnect corner. These corners are obtained by setting all relevant interconnect values to a maximum likely deviation (usually ±3σ). The two cell models are evaluated at the worst and beat combination of PVT (process, voltage, and temperature). The fast case is normally a fast process, high voltage, and cold temperature (for CMOS), and the slow case is slow process, low voltage, and high temperature. However, this approach does not address intra-chip variation at all, as it assumes all nets and cells scale exactly the same way.
Intra-chip variations, which are smaller than inter-chip variation, but are still present in a chip, are difficult to consider using traditional approaches. Analog designers have looked at this in detail, but in digital designs simpler methods are used. The major worry is that problems may arise if the clock and data signals do not track precisely. One technique, called 4 corner analysis, examines setup and hold times in fast and slow process conditions. In each of these four cases, the launching clock skew, the logic delay, and the receiving clock skew are set to their most pessimistic values.
Another technique for addressing this problem is called 6 corner analysis. It depends on classifying every gate and net as clock or data. The six corner cases that are then analyzed are when clock and data are both maximally slow; clock is maximally slow and data is almost as slow; and data is maximally slow and clock is almost as slow. The 3 corresponding cases with fast instead of slow are also considered. A complete timing analysis is done in each case. This approach assumes that clock network delays will track much more closely than data delays in general. This in turn requires that the clock network be built with this goal in mind. This is not a serious restriction if the clock network is built from the ground up, but is hard to enforce in an era of discrete electronic blocks, each with their own clocking structure.
One big problem with worst case analysis is that it is too conservative. It is extremely unlikely to have a 3σ variation on each of 30 dimensions. Without further analysis, however, we cannot tighten this bound, however, since it is possible that at least some critical paths axe determined by only one process dimension (say metal-1 resistance). Then a 3σ variation could in fact occur with significant probability.
The other problem is that corner analysis is not conservative enough, or in other words it can miss real errors. Take, for example, a flip flop where the data line is dominated by metal-1 delay and the clock line by metal-2 delay. Then the worst case for setup is when metal-1 is slow and metal-2 is fast. The worst case for hold time is when metal-1 is fast and metal-2 is slow. Neither of these two cases is found by either a (best, worst), a 4 corner, or a 6 corner analysis.
These different sources of variation into are taken into account by accounting for deterministic local variation. For example, one such effect is the proximity effect, where neighboring conductors affect the line width and spacing. OPC (Optical Proximity Correction) tries to correct this, but will not succeed completely. Likewise, there is a deterministic component to thickness that is controlled by the local density. Metal fill will try to fix this, but will also not succeed completely. These effects can be modeled straightforwardly, at least in flat extraction. For example, a possible approach includes computing the nominal width of each conductor from the neighboring width/spaces (the residual expected after OPC should be used for this correction); computing the nominal thickness of each conductor and ILD from the local density map for that layer; and deriving the R and C values from the local width and thickness.
However, if a block is extracted in isolation, the average local metal density is not known for features near the sides or corners. Furthermore, even after compensation for deterministic effects, there will still be wafer to wafer differences due to exposure differences, initial metal deposition thickness variation, non-flat wafers, and so on. Traditional approaches also require multiple runs of extraction and timing analysis to catch both the errors due to signals that are too fast and the errors due to signals that are too slow. Yet another problem is that since existing methods consider only one process point, either a net is critical or it is not. There is no way to know how much the improvement of a non-critical net is worth using existing methods.